This invention relates generally to programmable memories, and more particularly the invention relates to programming circuitry for EEPROM devices.
In the programming of electrical memories such as PROMs and EEPROMs a programming voltage in the order of 20 volts is required. With PROM devices an external power source is utilized. However, the programming of EEPROMs is accomplished using the chip operating voltage, typically 5 volts, with a high-voltage generator circuit in the chip developing the requisite programming voltage. In programming mode operation, a selected word line is raised to the programming voltage level sequentially by using a charge pump. See Brahmbhatt, U.S. Pat. No. 4,442,481 for "Low Power Decoder Circuit," and Gupta, U.S. Pat. No. 4,511,811 for "Charge Pump for Providing Programming Voltage to the Word Lines in a Semiconductor Memory Array."
Copending Brahmbhatt application Ser. No. A-46290, filed concurrently herewith, for EEPROM PROGRAMMING SWITCH OPERABLE AT LOW V.sub.CC, uses native transistors in charge pump circuitry, thus reducing the voltage drop across the transistors. However, bias means is required with the native transistors in a charge pump circuit to prevent the native transistors from operating in a depletion mode. This increases the circuit complexity.